The present invention relates to a semiconductor memory device and, more particularly, to a circuit for preventing a memory cell write error in an SRAM (Static Random Access Memory).
FIG. 6 shows a general SRAM 20.
In FIG. 6, in order to access a memory cell of a memory cell array 1, an address signal ADD is input to an address buffer 2, and the address buffer 2 supplies address values to column and row address decoders 3 and 4. The column address decoder 3 decodes the supplied address value to output a selection signal 12 for selecting one word line to the memory cell array 1. The row address decoder 4 decodes the supplied address value to output a selection signal 13 for selecting a bit line pair to a bit line controller 5.
The bit line controller 5 connects the selected bit line pair to a data input or output buffer 6 or 7 in response to the signal from the row address decoder 4. In the arrangement shown in FIG. 6, a signal for externally inputting/outputting data also serves as an I/O signal. A precharge circuit 8 charges a bit line pair to a predetermined potential in accordance with an equalization signal EQ generated by an address transfer detector (ATD) 9 in a read from a memory cell.
Reference symbol /WE denotes a write/read mode setting signal (to be referred to as a write enable signal) which represents a read mode at high level, and a write mode at low level; and /CS, a chip selection signal which activates the SRAM 20 at low level, and inactivates the SRAM 20 at high level.
When the SRAM 20 is mounted on one chip, the address signal ADD, the data input/output signal I/O, the write enable signal /WE, and the chip selection signal /CS are input outside the chip.
FIG. 7 shows the memory cell array 1, the bit line controller 5, and the precharge circuit 8. The bit line controller 5 generally includes a sense amplifier, write buffer, and the like, but only a column switch is illustrated in the controller 5 in FIG. 7 for descriptive convenience. FIG. 9 shows the arrangement of a memory cell M1. Memory cells M1 to M12 have the same arrangement.
The memory cell array 1 comprises a plurality of word lines W1, W2, . . . , Wn (to be referred to as Wn), pairs of bit lines D1 and /D1, D2 and /D2, . . . , Dn and /Dn (to be referred to as Dn and /Dn) perpendicular to the word lines Wn, and the memory cells M1, M2, . . . , M12 formed at intersections of the word lines Wn and the pairs of bit lines Dn and /Dn. The precharge circuit 8 is constituted by sets of three p-type (p-channel) transistors Q1, Q2, and Q3, Q4, Q5, and Q6, . . . , Q10, Q11, and Q12 in units of bit line pairs, and each set of three transistors is connected to one terminal of the pair of bit lines Dn and /Dn. The other terminal of the pair of bit lines Dn and /Dn is connected to the above-described bit line controller 5.
The word line Wn is connected to the column address decoder 3 shown in FIG. 6 and receives the word line selection signal 12. The bit line controller 5 connects the selected pair of bit lines Dn and /Dn to internal data buses DB and /DB, respectively, in response to the bit line selection signal 13 from the row address decoder 4. The internal data buses DB and /DB are respectively connected as data input and output signals DIN and DOUT to the data input and output buffers 6 and 7 in FIG. 6. As shown in FIG. 9, each of the memory cells M1 to M12 is made up of load resistors R1 and R2, and four n-type transistors Qa to Qd.
In the memory array having the arrangement shown in FIG. 6, data held by the memory cells M1 to M12 between adjacent bit line pairs are undesirably inverted by parasitic capacitances (to be referred to as line capacitances C1, C2, . . . , Cn) between the parallel pairs of bit lines Dn and /Dn in a write to the memory cells M1 to M12. This phenomenon will be called "a write error" of the memory cell and explained with reference to timing charts in FIGS. 8A to 8H.
First, the initial write states of the memory cells M1 to M12 in the memory cell array of FIG. 7 are assumed as follows:
Memory cell M1: D1-side potential is at high level, and /D1-side potential is at low level. PA1 Memory cell M2: D1-side potential is at low level, and /D1-side potential is at high level. PA1 Memory cell M4: D2-side potential is at high level, and /D2-side potential is at low level. PA1 Memory cell M7: D3-side potential is at low level, and /D3-side potential is at high level. PA1 Memory cell M8: D3-side potential is at high level, and /D3-side potential is at low level.
More specifically, assume that "1"s are written in the memory cells M1, M4, and M8, and "0"s are written in the memory cells M2 and M7, respectively. A description of the write states of the remaining memory cells will be omitted for convenience. A target write memory cell is M4. In the following description, "high level" means a power supply potential, and "low level" means a ground potential (0 V).
When the address signal ADD changes (FIG. 8A), the word line W1 corresponding to the memory cell M4 is selected to high level, and other word lines W2 and W3 are kept unselected at low level. The pairs of bit lines D2 and /D2 corresponding to the memory cell M4 is selected.
Since the word line W1 is selected by the address signal ADD before the write enable signal /WE shown in FIG. 8B changes to a write mode (low level), the bit lines D1 and /D1 are respectively at high and low levels in accordance with the write state of the memory cell M1 (FIG. 8E). Similarly, the bit lines D2 and /D2 are respectively at high and low levels in accordance with the write state of the memory cell M4 (FIG. 8D). The bit lines D3 and /D3 are respectively at low and high levels in accordance with the write state of the memory cell M7 (FIG. 8F).
If the value held by the data input buffer 6 is "0", when the write enable signal /WE changes to low level to set a write mode (timing T1 in FIG. 8B), the internal data bus DB which is outputting read data "1" changes from high level to low level, and /DB changes from low level to high level. The bit line D2 changes from high level to low level, and the bit line /D2 changes from low level to high level (FIG. 8D).
The value "0" of the data input signal DIN at timing T1 shown in FIG. 8C is not a value to be written in the memory cell M4, but a value left in a previous write. A value to be written in the memory cell M4 is input to the data input buffer 6 at timing T2. If this value is "1", the potentials of the bit lines D2 and /D2 are inverted again (FIG. 8D). Then, a write to the memory cell M4 is complete.
At timing T1, the bit line /D1 falls to a potential lower than the low level, i.e., a negative potential by the line capacitance C2 under the influence of a change of the bit line D2 from high level to low level, as shown in FIG. 8E. This may invert data of the unselected memory cell M2, as shown in FIG. 8G.
Operation of the memory cell M2 at this time will be explained with reference to FIG. 9. Although the gate potential of the transistor Qc in the memory cell M2 is at low level, the bit line /D1 falls to a negative potential exceeding the threshold voltage, thereby turning on the transistor Qc. The memory cell M2 changes from high level as the initial potential of the bit line /D1 side to low level to invert data of the memory cell M2.
Similarly, at timing T2, data of the memory cell M8 may be inverted as shown in FIG. 8H. That is, D3 falls to a potential lower than the low level, i.e., a negative potential by the line capacitance C4 under the influence of a change of the bit line /D2 from high level to low level, thus inverting data of the memory cell M8.
As described above, a write to the memory cell M4 may cause write errors in the memory cells M2 and M8 connected to the adjacent pairs of bit lines D1 and /D1 and D3 and /D3.
Various parasitic capacitances accompany the bit line and are shown in FIG. 10. FIG. 10 shows the schematic section of the bit line. The parasitic capacitances include the parasitic capacitance of each bit line, and the parasitic capacitances between upper and lower interconnections and a substrate and between bit lines. When a parasitic capacitance between adjacent bit lines is larger than those of the upper and lower bit lines, a write error more likely occurs.
A technique for preventing this write error is disclosed in Japanese Patent Laid-Open No. 7-192473. A conventional write error prevention circuit will be described with reference to FIGS. 11 and 12A to 12H. The same reference numerals as in FIGS. 7 and 8A to 8H denote the same parts, and a description thereof will be omitted. Assume that the initial states of respective memory cells and a data input buffer 6, and a target write memory cell are also the same as in FIGS. 7 and 8A to 8H for the sake of descriptive convenience.
In an SRAM in FIG. 11, a write error prevention circuit 10 is arranged between a memory cell array 1 and a precharge circuit 8. The write error prevention circuit 10 is constituted by n-type transistors Q13 and Q14, Q15 and Q16, . . . , Q19 and Q20 formed in units of bit line pairs, and a p-type transistor Q21. The n-type transistors Q13 to Q20 have gates and drains connected to the drain of the p-type transistor Q21 via a charge control line 10a, and sources connected to respective bit lines. The gate of the p-type transistor Q21 receives the write enable signal /WE.
Operation of the conventional SRAM having this arrangement will be described with reference to FIGS. 12A to 12H.
Similar to FIG. 7, when the write enable signal /WE changes from high level to low level at timing T1 in FIG. 12B, the SRAM changes from a read mode to a write mode. The p-type transistor Q21 is turned on to charge the drains and gates of the n-type transistors Q13 to Q20 to high level via the charge control line 10a and turn on the transistors Q13 to Q20. Then, the low-level potential of each pair of bit lines Dn and /Dn is charged. The charge potential is determined by the abilities of the n-type transistors Q13 to Q20.
At the same time as this charge, the internal data buses DB and /DB change to change the bit line D2 from high level to low level and the bit line /D2 from low level to high level (FIG. 12D). In the circuit of FIG. 7, the bit line /D1 falls to a negative potential under the influence of the line capacitance C2. However, this conventional circuit prevents the bit line /D1 from falling to a negative potential by slightly precharging the bit line /D1 (FIG. 12E).
Since charge continues while the write enable signal /WE is at low level, the bit line D3 is prevented from falling to a negative potential (FIG. 12F) when the data input signal DIN to be written in the memory cell M4 is confirmed (at timing T2 in FIG. 12C).
Since the bit lines /D1 and D3 do not fall to a negative potential at timings T1 and T2, no write error occurs in the adjacent memory cells M2 and M8 (FIGS. 12G and 12H).
In the circuit of FIG. 7, a write error is generated in a write to a memory cell. In the circuit of FIG. 11 which solves this problem, the pair of bit lines Dn and /Dn is being charged while the write enable signal /WE is generated. More specifically, since the n-type transistors Q13 to Q20 and the p-type transistor Q21 are always ON during a memory cell write mode, a stationary current flows through the write error prevention circuit 10 and the pair of bit lines Dn and /Dn to increase the power consumption.